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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:17:58 11/23/2017 
-- Design Name: 
-- Module Name:    xianshi - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity xianshi is
          Port ( clk : in STD_LOGIC;
                 h1 : in STD_LOGIC_vector(3 downto 0);
                 h0 : in STD_LOGIC_vector(3 downto 0);
                 m1 : in STD_LOGIC_vector(3 downto 0);
                 m0 : in STD_LOGIC_vector(3 downto 0);
                 s1 : in STD_LOGIC_vector(3 downto 0);
                 s0 : in STD_LOGIC_vector(3 downto 0);
                 sel : out STD_LOGIC_vector(7 downto 0);
                 seg : out STD_LOGIC_vector(6 downto 0));
end xianshi;
architecture Behavioral of xianshi is
signal n:integer range 0 to 24000:= 1;
signal set:std_logic_vector(2 downto 0):="000";
signal clk_1kHz:STD_LOGIC:='0';
signal d:STD_LOGIC_vector(3 downto 0):="0000";
begin


process(clk)
begin
if clk'event and clk='1' then
if n=24000 then
n<=1;
clk_1kHz<= not clk_1kHz;
else
n<=n+1;
end if;
end if;
end process;
process(clk_1kHz)
begin
if clk_1kHz'event and clk_1kHz='1' then
if set = "111" then
set<="000";
else
set<=set+1;
end if;
end if;
end process;
process(set,h1,h0,m1,m0,s1,s0)
begin
case set is
when"000"=> d<=h1;
when"001"=> d<=h0;
when "010"=> d<= "1111";
when "101"=> d<= "1111";
when"011"=> d<=m1;
when"100"=> d<=m0;
when"110"=> d<=s1;
when"111"=> d<=s0;
when others=> seg<="0000001";
end case;
case set is
when"000"=> sel<="01111111";
when"001"=> sel<="10111111";
when"010"=> sel<="11011111";
when"011"=> sel<="11101111";
when"100"=> sel<="11110111";
when"101"=> sel<="11111011";
when"110"=> sel<="11111101";
when others=> sel<="11111110";
end case;
case d is
when "0000"=> seg<="0000001";
when "0001"=> seg<="1001111";
when "0010"=> seg<="0010010";
when "0011"=> seg<="0000110";
when "0100"=> seg<="1001100";
when "0101"=> seg<="0100100";
when "0110"=> seg<="0100000";
when "0111"=> seg<="0001111";
when "1000"=> seg<="0000000";
when "1001"=> seg<="0000100";
when "1111"=> seg<="1111110";
when others => null;
end case;
end process;
end Behavioral;
